1. Field of the Invention
The invention relates to a DC-DC converter, and more particularly to a DC-DC converter using an N-type FET in a main switching device.
2. Description of the Related Art
As one of the methods for improving the efficiency in a DC-DC converter of a switching regulator system, it is proposed to use an N-type FET in a main switching device. As compared with use of a P-type FET in a main switching device, conduction resistance can be decreased to about 42% if the size is the same, which contributes greatly to improvement of efficiency in the DC-DC converter.
To use an N-type FET as a main switching device of a DC-DC converter, the gate driving voltage of the N-type FET is required to be higher than the input voltage to the source terminal. As means for generating such high gate driving voltage, it is general to use a charge pump circuit using an FET of a synchronous rectifier circuit.
FIG. 15 is a circuit diagram of a DC-DC converter 100 using a charging pump circuit of prior art. The DC-DC converter 100 is built in an electronic appliance (such as a notebook computer), and converts a power source input voltage Vin from a battery not shown, and outputs an output voltage Vout for operating the CPU and peripheral devices.
The DC-DC converter 100 is composed of a control part 102 formed on a one-chip semiconductor integrated circuit, and a plurality of external devices.
A first drive signal DH1 of the control part 102 is supplied to a gate terminal of a main NMOS transistor FET1, and the power source input voltage Vin is inputted to a drain terminal of the main NMOS transistor FET1. A source terminal of the main NMOS transistor FET1 is connected to a drain terminal of a synchronous rectifier NMOS transistor FET2. A second drive signal DL1 of the control part 102 is supplied to a gate terminal of the synchronous rectifier NMOS transistor FET2, and a source terminal of the synchronous rectifier NMOS transistor FET2 is connected to a grounding potential.
A source terminal of the main NMOS transistor FET1 is connected to an output terminal 103 by way of a choke coil L1. The output terminal 103 is connected to the grounding potential by way of a smoothing capacitor C1.
The control part 102 includes potential resistances R1, R2, an error amplifier ERA1, a triangular wave oscillator OSC1, a PWM comparator PWM1, and drivers DVH1, DVL1, and outputs a first drive voltage DH1 and a second drive signal DL1, and thereby controls the main NMOS transistor FET1 and the synchronous rectifier NMOS transistor FET2.
In the control part 102, the output voltage Vout is divided by the potential resistances R1, R2, and the divided voltage is inputted to an inverting input terminal of an error amplifier ERA1. A reference voltage e1 is inputted to a non-inverting input terminal of the error amplifier ERA1. The error amplifier ERA1 compares the divided voltage depending on the output voltage Vout and the reference voltage e1, and amplifies the voltage difference, and outputs an output signal Vop1.
FIG. 16 is a timing chart showing the operation waveform in the control part 102.
In the control part 102, the voltage of an output signal Vop1 of the error amplifier ERA1 is large in variation when the voltage difference is greater between the divided voltage depending on the output voltage Vout (divided voltage by potential resistances R1, R2) and the reference voltage e1, and is small in variation when the voltage difference is smaller between the divided voltage and the reference voltage e1.
The PWM comparator PWM1 sets an output signal Q1 at a high level when the triangular wave signal is lower than the output voltage Vop1 of the error amplifier ERA1, and sets Q1 at a low level when the triangular wave signal is higher than the output voltage Vop1. Therefore, when the voltage of the output voltage Vop1 of the error amplifier ERA1 elevates, the output pulse width of the PWM comparator PWM1 (the pulse width for setting the output signal Q1 at a high level) becomes longer.
The output signal Q1 of the PWM comparator PWM1 is inputted to the gate terminal of the main NMOS transistor FET1 through the driver DVH1 as the first drive voltage DH1. Accordingly, when the output pulse width of the PWM comparator PWM1 becomes longer, the conduction time of the main NMOS transistor FET1 becomes longer, and to the contrary, when the output pulse width of the PWM comparator PWM1 becomes shorter, the conduction time of the main NMOS transistor FET1 becomes shorter.
In the DC-DC converter 100, conduction and non-conduction of the main NMOS transistor FET1 are controlled so that the output voltage Vout may be a constant voltage determined by the reference voltage e1 and the potential resistances R1, R2, depending on the output signal Q1 of the PWM comparator PWM1.
The PWM comparator PWM1 outputs an output signal XQ1 for inverting the logic level of the output signal Q1. That is, the output signals Q1, XQ1 are outputted from the PWM comparator PWM1 as mutually complementary pulse signals. The output signal XQ1 from the PWM comparator PWM1 is supplied in the gate terminal of the synchronous rectifier NMOS transistor FET2 as the second drive signal DL1 by way of the driver DVL1.
Therefore, the synchronous rectifier NMOS transistor FET2 does not conduct while the main NMOS transistor FET1 is conducting, and the synchronous rectifier NMOS transistor FET2 conducts while the main NMOS transistor FET1 is not conducting. That is, by the first drive voltage DH1 and the second drive voltage DL1 outputted from the control part 102, the main NMOS transistor FET1 and the synchronous rectifier NMOS transistor FET2 conduct alternately.
By the switching operation of the main NMOS transistor FET1, the output current of the main NMOS transistor FET1 is smoothed by the choke coil L1 and a smoothing capacitor C1. While the main NMOS transistor FET1 is conducting, the power source input voltage Vin is supplied to the smoothing circuit composed of the choke coil L1 and the smoothing capacitor C1 by way of main NMOS transistor FET1. When the main NMOS transistor FET1 is not conducting, the electromagnetic gain energy accumulated in the choke coil L1 while the main NMOS transistor FET1 is conducting is released to the output terminal 103 side.
The output voltage Vout of the output terminal 103 is expressed in the following formula.Vout=Vin×Ton/(Ton+Toff)where Ton is the conducting period of the main NMOS transistor FET1, and Toff is the non-conducting period of the main NMOS transistor FET1.
Therefore, if the power source input voltage Vin fluctuates due to a battery consumption or an operating environment of electronic appliances, by controlling the duty cycle of the output signal Q1, it may be compensated so that the output voltage Vout may be kept at a constant voltage.
Since an N type FET is used in the main NMOS transistor FET1 of the DC-DC converter 100, a voltage higher than the power source input voltage Vin is needed as the first drive voltage DH1 for driving the main NMOS transistor FET1. Accordingly, in the DC-DC converter 100, by making use of the phenomenon of amplitude of the source potential within the power source input voltage Vin when the main NMOS transistor FET1 conducts and does not conduct, the driving voltage of the gate terminal of the main NMOS transistor FET1 is generated by the charge pump.
The output signal Q1 of the PWM comparator PWM1 is inputted in the gate terminal of the main NMOS transistor FET1 as the first drive voltage DH1 through the driver DVH1, and the output signal XQ1 is supplied in the gate terminal of the synchronous rectifier NMOS transistor FET2 as the second drive voltage DL1 through the driver DVL1.
Between the source and drain of the main NMOS transistor FET1, a series circuit of a diode D1 and a capacitor C2 is connected in parallel. Herein, the cathode of the diode D1 is connected to the capacitor C2, and its junction is connected to the power source terminal of the driver DVH1.
In this DC-DC converter 100, while the main NMOS transistor FET1 is not conducting and the synchronous rectifier NMOS transistor FET2 is conducting, the source potential of the main NMOS transistor FET1 is a grounding potential. At this time, a current flows into the capacitor C2 by way of the diode D1, and the capacitor C2 is charged until its voltage becomes equal to the power source input voltage Vin.
At the next transition, the main NMOS transistor FET1 is conducting and the synchronous rectifier NMOS transistor FET2 is not conducting, the source potential of a main NMOS transistor FET1 elevates, and the potential of the terminal BOOST capacitively coupled by the capacitor C2 becomes higher than the power source input voltage Vin. A voltage higher than the power source input voltage Vin is applied to the gate terminal of the main NMOS transistor FET1 by way of the driver DVH1 having the power source terminal connected to the terminal BOOST, and therefore the main NMOS transistor FET1 conducts completely.
At this time, the diode D1 prevents the charge of the capacitor C2 of which voltage is higher than the power source input voltage Vin from flowing reversely into the power source input voltage Vin. The diode D1 is generally realized by a Schottky diode of which forward electromotive force Vf is smaller than that of an ordinary diode.
In the diode D1, however, since the power consumption occurs for the portion of forward electromotive force Vf when charging the capacitor C2, the efficiency of the DC-DC converter is lowered. Further, for the portion of forward electromotive force Vf, the potential charged in the capacitor C2 is lowered. Assuming to incorporate the diode D1 at the control circuit side of one-chip semiconductor device, the existing process for forming a Schottky diode is complicated.